1. Field of the Invention
The present invention relates to a technique for protecting an integrated circuit from electrostatic discharge.
2. Description of the Prior Art
The protection of integrated circuits from electrostatic discharge (ESD) has become a significant aspect of IC design. The vulnerable points usually include the input terminals, through which an electrostatic discharge event can damage transistors or other circuit components. The advent of insulated gate field effect transistor (IGFET) circuitry has increased the problem, due to their very high impedance input circuits, which do not readily allow an electrostatic charge to dissipate, except by breaking down the gate insulator. Various techniques have been developed to deal with the ESD problem; see, for example, "The Effects of Electrostatic Discharge on Microelectronic Devices - A Review", IEEE Transactions on Industry Applications, Vol. 1A-20, W. D. Greason et al, pages 247-252 (1984).
One ESD protection technique utilized with complementary metal oxide silicon (CMOS) integrated circuits uses two diodes connected to an IC input pad, usually through a resistor. One of the diodes is connected to the positive power supply (VCC or VDD) terminal, and the other diode is connected to the ground (VSS) power supply terminal. During normal operation, when the power supply voltages are present, the diodes do not conduct. However, when a voltage in excess of a p-n junction voltage drop (about 0.7 volts) appears, conduction occurs through the diode forward biased thereby, which protects the IC circuitry. The protection is obtained even if the IC is not connected to the power supply, due to direct or capacitive coupling from each power supply terminal to the substrate of the integrated circuit.
In a typical prior art CMOS integrated circuit diode protection configuration as shown in FIG. 1, the pad (10) is connected by a conductor (not shown) to the circuit input. It is also connected via contact windows (13, 14) through an insulating layer (not shown) to n and p regions (11, 12) that form diodes with the underlying semiconductor regions of opposite conductivity (not shown), which are connected to the power supplies (VCC, VSS). Each diode is partially surrounded by a guardring (15, 16) of semiconductor material having opposite conductivity as the associated top diode regions (11, 12). The guardrings are connected to the power supplies via contact windows (17, 18) through an overlying insulator. The guardrings serve to prevent minority carriers from being injected into the substrate when a diode conducts, thereby helping to avoid latchup. The protection diodes and guardrings are spaced apart from the input pads in prior art designs, which takes up considerable IC area, as shown in FIG. 1.
It is also known to use a field effect transistor as the protection element; see FIG. 2. In that technique, the bondpad (20) and gate (22) are connected together, and to the drain (21) through contact windows (24). The source (23) is then connected to the more negative power supply voltage (VSS). In another prior art technique used with bipolar IC designs, it is known to clamp excessive input voltage signals (not of ESD origin) by placing an input "beam lead" conductor over a diode. thereby conserving space. The conductor was typically formed by electroplating gold, and then extended off of the chip for connection to external circuitry. Furthermore, in the bipolar case a single diode was typically sufficient, since the input bipolar transistor itself provided protection for the opposite polarity voltage, due to its base-emitter junction.